This invention relates to a semiconductor device and a method of manufacturing the semiconductor device and, in particular, to a semiconductor device having a multilayer wiring and a manufacturing method thereof.
In recent wiring technique, multilayer of wiring has been carried out in the technical field of semiconductor devices with high density and with large-scale integration thereof. The large subjects for the multilayer of wiring are the improvement of coverage in wiring for contact sections and the improvement of forming methods of insulating films for wiring layers.
Measures for the coverage in wiring for the contact sections are disclosed, for example, in Japanese Unexamined Patent Prepublication No. 87848/83 and in Japanese Unexamined Patent Prepublication No. 57648/85. The measures are methods of embedding conductors in contact holes and will later be described in conjunction with FIGS. 1(A) through 1(E). However, various problems occur in these methods when the number of the wiring layers increases. That is, as will later be described in conjunction with FIG. 2, when the number of the wiring layers increases, an interlayer insulating region becomes thick. As a result, it is difficult to embed the conductors in the contact holes if the conductors are not made of material which satisfies a severe condition. In addition, the embedded conductors have a high electric resistance which results in hurdles on the road to high speed. Furthermore, these methods are disadvantageous in that they comprise a lot of steps. This is because both contact hole boring processes and embedding processes are required for each wiring layer.
On the other hand, measures for forming methods of the insulating films for the wiring layers are disclosed, for example, by A. Shinohara et al in a paper submitted to "Extended Abstract of the 17th Conference on Solid State Devices and Materials", Tokyo, 1985, pages 29-32 under the title of "A New Self-Aligned Contact Technology for LDD MOS Transistors" and in Japanese Unexamined Patent Prepublication No. 43149/87. The measures are methods of forming side-wall insulating films on a side surface of a wiring layer and will later be described in conjunction with FIGS. 3(A) through 3(F). However, in these method, when a contact hole for an upper wiring layer is required in a position without a lower wiring layer, the contact hole must be necessarily bored by using a photo resist or the like as a mask. As a result, it is impossible to reduce the number of the contact hole making processes. In addition, these methods are defective in that it has no effect to improve coverage of wiring in the contact hole when the interlayer insulating region becomes thick.